1. Field of the Invention
This invention relates to dynamic semiconductor memory systems. More particularly, this invention relates to a novel standby driving circuit for refreshing the information stored in a dynamic semiconductor memory system during power failure.
2. Description of the Prior Art
Dynamic semiconductor memory systems are well-known. The semiconductor industry is presently supplying packaged modules which may be arranged in X, Y and Z memory planes to create solid state memories for the largest and fastest commercial computers being made today. One disadvantage of a dynamic semiconductor memory system is that it is a volatile medium, i.e., there is a tendency for the information which is stored in the memory to be lost during power failures. Also, such memories have destructive readout (DRO) properties and during normal read-in and read-out operations, the information must be resupplied or rewritten into the semiconductor memory. Furthermore, dynamic semiconductor memories tend to lose their information with passage of time and therefore must be periodically "refreshed."
Heretofore, it was known that a dynamic semiconductor memory system could be refreshed by periodically interrupting the normal read and write operations and supplying a refresh address or refresh signal on the address lines of the semiconductor matrix. Heretofore, it also has been common practice to provide an independent and secondary refresh address driving means which is turned on at the time power failure is sensed. Such prior art standby refresh address driving systems require a time lag to become operable and as a result the memory may lose the information which is supposed to be refreshed. Further, standby refresh address power driving systems have heretofore required an inordinately large amount of power to sustain or refresh the dynamic semiconductor memory which has resulted in rapid drain of the standby power source.